// SPDX-License-Identifier: (GPL-2.0+ or MIT)

#ifndef _DT_BINDINGS_CLK_SPACEMIT_K1X_H_
#define _DT_BINDINGS_CLK_SPACEMIT_K1X_H_

/*
    !!! clk list must start with CLK_PLL1_2457P6 !!!
    in order to differ from spl clk list, CLK_PLL1_2457P6 start with 40.
*/
#define CLK_PLL1_2457P6          40
#define CLK_PLL2                 41
#define CLK_PLL3                 42
#define CLK_PLL1_D2              43
#define CLK_PLL1_D3              44
#define CLK_PLL1_D4              45
#define CLK_PLL1_D5              46
#define CLK_PLL1_D6              47
#define CLK_PLL1_D7              48
#define CLK_PLL1_D8              49
#define CLK_PLL1_D11             50
#define CLK_PLL1_D13             51
#define CLK_PLL1_D23             52
#define CLK_PLL1_D64             53
#define CLK_PLL1_D10_AUD         54
#define CLK_PLL1_D100_AUD        55
#define CLK_PLL2_D1              56
#define CLK_PLL2_D2              57
#define CLK_PLL2_D3              58
#define CLK_PLL2_D4              59
#define CLK_PLL2_D5              60
#define CLK_PLL2_D6              61
#define CLK_PLL2_D7              62
#define CLK_PLL2_D8              63
#define CLK_PLL3_D1              64
#define CLK_PLL3_D2              65
#define CLK_PLL3_D3              66
#define CLK_PLL3_D4              67
#define CLK_PLL3_D5              68
#define CLK_PLL3_D6              69
#define CLK_PLL3_D7              70
#define CLK_PLL3_D8              71
#define CLK_PLL1_307P2           72
#define CLK_PLL1_76P8            73
#define CLK_PLL1_61P44           74
#define CLK_PLL1_153P6           75
#define CLK_PLL1_102P4           76
#define CLK_PLL1_51P2            77
#define CLK_PLL1_51P2_AP         78
#define CLK_PLL1_57P6            79
#define CLK_PLL1_25P6            80
#define CLK_PLL1_12P8            81
#define CLK_PLL1_12P8_WDT        82
#define CLK_PLL1_6P4             83
#define CLK_PLL1_3P2             84
#define CLK_PLL1_1P6             85
#define CLK_PLL1_0P8             86
#define CLK_PLL1_351             87
#define CLK_PLL1_409P6           88
#define CLK_PLL1_204P8           89
#define CLK_PLL1_491             90
#define CLK_PLL1_245P76          91
#define CLK_PLL1_614             92
#define CLK_PLL1_47P26           93
#define CLK_PLL1_31P5            94
#define CLK_PLL1_819             95
#define CLK_PLL1_1228            96
#define CLK_SLOW_UART1           97
#define CLK_SLOW_UART2           98
#define CLK_UART1                99
#define CLK_UART2                100
#define CLK_UART3                101
#define CLK_UART4                102
#define CLK_UART5                103
#define CLK_UART6                104
#define CLK_UART7                105
#define CLK_UART8                106
#define CLK_UART9                107
#define CLK_GPIO                 108
#define CLK_PWM0                 109
#define CLK_PWM1                 110
#define CLK_PWM2                 111
#define CLK_PWM3                 112
#define CLK_PWM4                 113
#define CLK_PWM5                 114
#define CLK_PWM6                 115
#define CLK_PWM7                 116
#define CLK_PWM8                 117
#define CLK_PWM9                 118
#define CLK_PWM10                119
#define CLK_PWM11                120
#define CLK_PWM12                121
#define CLK_PWM13                122
#define CLK_PWM14                123
#define CLK_PWM15                124
#define CLK_PWM16                125
#define CLK_PWM17                126
#define CLK_PWM18                127
#define CLK_PWM19                128
#define CLK_SSP3                 129
#define CLK_RTC                  130
#define CLK_TWSI0                131
#define CLK_TWSI1                132
#define CLK_TWSI2                133
#define CLK_TWSI4                134
#define CLK_TWSI5                135
#define CLK_TWSI6                136
#define CLK_TWSI7                137
#define CLK_TWSI8                138
#define CLK_TIMERS1              139
#define CLK_TIMERS2              140
#define CLK_AIB                  141
#define CLK_ONEWIRE              142
#define CLK_SSPA0                143
#define CLK_SSPA1                144
#define CLK_DRO                  145
#define CLK_IR                   146
#define CLK_TSEN                 147
#define CLK_IPC_AP2AUD           148
#define CLK_CAN0                 149
#define CLK_CAN0_BUS             150
#define CLK_WDT                  151
#define CLK_RIPC                 152
#define CLK_JPG                  153
#define CLK_JPF_4KAFBC           154
#define CLK_JPF_2KAFBC           155
#define CLK_CCIC2PHY             156
#define CLK_CCIC3PHY             157
#define CLK_CSI                  158
#define CLK_CAMM0                159
#define CLK_CAMM1                160
#define CLK_CAMM2                161
#define CLK_ISP_CPP              162
#define CLK_ISP_BUS              163
#define CLK_ISP                  164
#define CLK_DPU_MCLK             165
#define CLK_DPU_ESC              166
#define CLK_DPU_BIT              167
#define CLK_DPU_PXCLK            168
#define CLK_DPU_HCLK             169
#define CLK_DPU_SPI              170
#define CLK_DPU_SPI_HBUS         171
#define CLK_DPU_SPIBUS           172
#define CLK_SPU_SPI_ACLK         173
#define CLK_V2D                  174
#define CLK_CCIC_4X              175
#define CLK_CCIC1PHY             176
#define CLK_SDH_AXI              177
#define CLK_SDH0                 178
#define CLK_SDH1                 179
#define CLK_SDH2                 180
#define CLK_USB_P1               181
#define CLK_USB_AXI              182
#define CLK_USB30                183
#define CLK_QSPI                 184
#define CLK_QSPI_BUS             185
#define CLK_DMA                  186
#define CLK_AES                  187
#define CLK_VPU                  188
#define CLK_GPU                  189
#define CLK_EMMC                 190
#define CLK_EMMC_X               191
#define CLK_AUDIO                192
#define CLK_HDMI                 193
#define CLK_CCI550               194
#define CLK_PMUA_ACLK            195
#define CLK_CPU_C0_HI            196
#define CLK_CPU_C0_CORE          197
#define CLK_CPU_C0_ACE           198
#define CLK_CPU_C0_TCM           199
#define CLK_CPU_C1_HI            200
#define CLK_CPU_C1_CORE          201
#define CLK_CPU_C1_ACE           202
#define CLK_PCIE0                203
#define CLK_PCIE1                204
#define CLK_PCIE2                205
#define CLK_EMAC0_BUS            206
#define CLK_EMAC0_PTP            207
#define CLK_EMAC1_BUS            208
#define CLK_EMAC1_PTP            209
#define CLK_SEC_UART1            210
#define CLK_SEC_SSP2             211
#define CLK_SEC_TWSI3            212
#define CLK_SEC_RTC              213
#define CLK_SEC_TIMERS0          214
#define CLK_SEC_KPC              215
#define CLK_SEC_GPIO             216

#define CLK_APB                  217

#define CLK_VCTCXO_24            218
#define CLK_VCTCXO_3             219
#define CLK_VCTCXO_1             220
#define CLK_PLL1                 221
#define CLK_32K                  222
#define CLK_DUMMY                223

#define CLK_MAX_NO               224


#endif /* _DT_BINDINGS_CLK_SPACEMIT_K1X_H_ */
